Low Power Instruction Fetch using Profiled Variable Length Instructions

Computer system performance is highly dependent on high access rate and low miss rate in the instruction cache, which also have implications on energy consumed by fetching instructions. Simulation experiments on a small scalar processor typical for embedded systems show that up to 20% of the overall processor energy is consumed in the instruction fetch path and that as much as 23% of the execution time is spent on instruction fetch. One way to increase the instruction memory bandwidth is to fetch more instructions on each access without increasing the bus width. We propose an extension of the normal RISC style ISA. The ISA is augmented with instructions of variable length, yielding a higher information density, without compromising programmability. Based on extensive profiling of dynamic instruction usage, in terms of instruction types and arguments of a set of SPEC CPU2000 applications, we present an extension scheme, using short, 8 and 16-bit instructions accompanied by lookup tables for used instruction argument combinations, that resides in the processor. In addition, we discuss introduced architectural extensions and implications experienced when enabling the fetch of four-byte wide chunks which can contain up to four instructions. Energy savings in instruction fetch and the rest of the processor are evaluated along with performance implications due to the property of variable length instructions using SimpleScalar and Wattch simulators. Our extension scheme with short instructions yields a 20-30% reduction in static memory usage, and simulations show that up to 60% of the dynamic executed instructions consist of short instructions. Throughout all executions, the programs experienced a reduction in instruction cache miss-rate. The overall energy savings are up to 15% for the entire data path and memory system, and up to 20% in the instruction fetch path alone.